This invention relates to a semiconductor integrated circuit device, such as a flash memory or the like, and to a data processing system, such as a digital still camera, in which such a semiconductor integrated circuit device is employed.
An example of a flash memory device has been disclosed in the 1994 Symposium on VLSI Circuits, Direst of Technical Papers, pp. 61-62.
In this flash memory, a state in which the threshold voltage of each of the memory cells included in the flash memory is high, and a state in which the threshold voltage thereof is low, can be defined as, for example, an erased state and a written (programmed) state, respectively. In this case, writing can be performed after erase operations have been performed collectively in word line units, for example. Upon completion of erase and write operations, the application of pulse-shaped voltages and a verify operation are repeatedly performed until a desired threshold voltage is acquired so that a change in threshold voltage is not increased undesirably.
When the application and transition of the voltage from the threshold voltage in the erased state to the threshold voltage in the written state has been completed. it is difficult to vary the threshold voltage as the threshold voltage approaches the written state. Therefore, the application of the same pulse width will lead to a state in which only the verify operation is being performed even though the threshold voltage changes very little. Therefore, when it is desired to perform writing using a fixed write voltage level, the pulse width is made long as the threshold voltage approaches the written state. The voltage may be gradually increased as an alternative to the gradual increase in pulse width.
High-accuracy writing has heretofore been realized so that a write level (equivalent to a verify word line voltage at writing) is set as, for example, 1.5V with respect to a power source voltage Vcc of, for example, 3.3V, and a write pulse or the threshold voltage of each memory cell varies over a range from 0.1V to 0.2V.
With respect to a power source voltage of, for example, 3.3V, a write level has heretofore been set practically to, for example, 1.5V, corresponding to about one half the power source voltage. One obtained by adding a difference in threshold voltage, for obtaining a current difference required to detect the voltage using a sense amplifier, to the voltage is defined as the minimum or lowest voltage (Vev) in an erased state. Upon erasing, the application of an erase pulse is controlled by detecting whether or not the threshold voltage of each memory cell has reached above Vev. A low voltage operation and high reliability can be achieved by lowering the write voltage and thereby reducing Vev to as low a level as possible.
However, the actual circumstances or fact is that the characteristic of each memory cell is varied by about three digits in the time required to reach a threshold voltage leading from an erased state to a written state when voltages to be applied upon writing are the same. When the writing of data into the corresponding memory cell is performed under such a condition, there may be cases where the threshold voltage results in 0V or less according to memory cells in the case of normal variations in characteristic of each memory cell unless a change in threshold voltage of the memory cell is set as a write pulse (width or voltage) that reaches 0.2V or less. The 3-digit variation results in about 3V if converted into a variation in equivalent threshold voltage. Thus, since the amount of change in threshold voltage per write pulse is equivalent to a change of 0.2V until the threshold voltage of a memory cell latest in written state reaches a written state, since the threshold voltage of a memory cell shortest in time required to bring it into the written state has led to the written state, it is necessary to apply a pulse 15 times if calculated simply. It is necessary to perform a verify operation for making a decision as to whether the threshold voltage has reached a desired value for each pulse. This has led to a lengthy overhead during the write time.
An object of the present invention is to speed up a write operation made to a non-volatile memory cell.
Another object of the present invention is to make the speeding up of a write operation made to a non-volatile memory cell compatible with a high reliability of data retention.
The above and other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical features disclosed in the present application will be described briefly as follows.
Namely, a semiconductor integrated circuit, such as a flash memory device, has a plurality of electrically erasable and programmable non-volatile memory cells and includes a control means for supplying a pulse-shaped voltage to each non-volatile memory cell until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control means has a first operating mode in which the amount of change in threshold voltage of each non-volatile memory cell, which varies each time the pulse-shaped voltage is applied thereto, is relatively large, and a second operating mode in which the amount of change in threshold voltage thereof is relatively small.
The amount of change in threshold voltage of each memory cell per pulse in a write voltage pulse or write voltage pulse train in a first operating mode (coarse write) and the amount of change in threshold voltage per pulse in a second operating mode (high-accuracy write) are defined as xcex94Vth1 and xcex94Vth2, for example, respectively. considering at this time where the difference (cell window) in voltage between the minimum threshold corresponding to an erased state in a threshold voltage distribution of a non-volatile memory cell and the maximum threshold corresponding to a written state in the threshold voltage distribution is fixed, then the number of pulses required to change the threshold voltage of each memory cell at xcex94Vth1 is smaller than that at xcex94Vth2. Therefore, the number of verify operations at the time that the first operating mode (xcex94Vth1) is used, is smaller than when the second operating mode (xcex94Vth2) is used. The time required to perform writing corresponds to the sum of the time required to change the threshold voltage of each memory cell itself and an overhead time,such as the time required to perform the verify operation. Thus, since a decrease in the number of verify operations results in a reduction in overhead, the write operation is speeded up as a whole.
It is desirable for the level (threshold voltage) to be written into a memory cell in the first operating mode to be higher than that in the second operating mode. Namely, a threshold voltage distribution in a written state,at xcex94Vth1 in which the amount of change in threshold voltage is relatively large, becomes greater than a threshold voltage distribution in a written state at xcex94Vth2 in the second operating mode. Thus, doing so is desired to avoid depleting. In other words, it is desired that a write verify voltage in the first operating mode (coarse write) be set higher than a write verify voltage in the second operating mode (high-accuracy write). Even if the cell window in the first operating mode is not set equal to that in the second operating mode, an erase level written into a memory cell in the first operating mode has a tendency to become higher than an erase level written into a memory cell in the second operating mode. Thus, the electric field between a floating gate and a semiconductor substrate of the memory cell written in the second write operating mode is lower than that of the memory cell written in the first operating mode at the time of information retention. Further, the information retention time of the memory cell written in the second write operating mode is longer than that of the memory cell written in the first operating mode. Namely, the memory cell written in the second operating mode exhibits an excellent information retention performance. In this sense, the second operating mode can be placed or defined as a high-accuracy write mode.
The control means can be provided with a rewrite control means for rewriting data written in the first operating mode in the second operating mode. Namely, after the data has been written into each memory cell in the first operating mode of short write time, it is renewed or rewritten in the second operating mode capable of narrowing the distribution of the threshold voltage of the memory cell. With respect to rewriting, the data is read from the corresponding memory cell and latched in its corresponding sense latch, and the latched data is defined as data to be written in the second operating mode.
The coarse write based on the first operating mode and the high-accuracy write based on the second operating mode can be controlled by switching according to conditions, such as address areas, the number of cumulatings for reprogramming, etc. as well as switching control on the rewriting executed in the first and second operating modes.
A memory mat exclusive to the coarse write and a memory mat exclusive to the high-accuracy write can be also dedicated.
The data to be written in the first operating mode may be set as binary data and the data to be written in the second operating mode may be set as multivalued data. At this time, the rewrite control means is capable of rewriting the binary data written in the first operating mode to the multivalued data in the second operating mode.
A semiconductor integrated circuit is able to have only the coarse write executed in the first operating mode as a writing mode. Namely, the semiconductor integrated circuit has a plurality of electrically erasable and programmable non-volatile memory cells and includes a control means for supplying a pulse-shaped voltage to each non-volatile memory cell until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. At this time, the control means controls the second threshold voltage to a voltage that falls within a range lower than or equal to a power source voltage and higher than or equal to one half the power source voltage.
According to another aspect or viewpoint of the semiconductor integrated circuit having only the coarse write mode as a writing mode, the control. means controls the second threshold voltage to a voltage ranging from below 3.3V to above 2V when the power source voltage is in the neighborhood of 3.3V.
At this time, the control means can set the amount of change in threshold voltage per pulse-shaped voltage to above 0.4V. According to a further aspect of the semiconductor integrated circuit, the control means can control the amount of change in threshold voltage per pulse-shaped voltage to above one third the difference between the first threshold voltage and the second threshold voltage.
According to a still further aspect of a semiconductor integrated circuit having only a rough or coarse write mode as a writing mode, the semiconductor integrated circuit having a memory array configuration, which is typified by a NAND type, has a plurality of electrically erasable and programmable non-volatile memory cells and a control means for supplying a pulse-shaped voltage to each non-volatile memory cell until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage, whereby a control voltage for turning on a non-selected non-volatile memory cell is supplied to the non-selected non-volatile memory cell at the time of a read operation. At this time, the control means controls the second threshold voltage so as to reach a voltage lying within a range in which the difference between the second threshold voltage and the control voltage is lower than or equal to the control voltage and is higher than or equal to one half the power source voltage. Alternatively, the control means controls the second threshold voltage so as to reach a voltage that falls within a range in which the difference between the second threshold voltage and the control voltage is lower than or equal to 3.3V and is higher than or equal to 2V.
As described above, the characteristic of each memory cell is varied by about three digits in the time required to reach the threshold voltage leading from the erased state to the written state when the voltages to be applied upon writing are the same. When the writing of data into the corresponding memory cell is performed under such a condition, it is considered that there may be cases where the threshold voltage results in 0V or less according to memory cells in the case of normal variations in characteristic of each memory cell unless a change xcex94Vth1 in threshold voltage of the memory cell is set as a write pulse (width or voltage) that reaches 0.2V or less. In order to write data at high speed at this time, the amount of change xcex94Vth1 per write pulse is increased by making the pulse width long or by raising the voltage. However, the memory cell is apt to deplete due to this increase. The write level is rendered high to avoid this. If the threshold voltage in the written state is set to about 2.0V when the power source voltage is about 3.3V, for example, then xcex94Vth1 can be set to 0.4V. Since the 3-digit variation referred to above is equivalent to a threshold voltage variation of 3V, assuming the existence of the 3-digit variation, the pulse may be applied eight times. Since the number of verify operations is reduced as much, the data can be written at high speed. Namely, the write level was intended to fall below xc2xd the power source voltage in the art, whereas it is set so as to fall above one half the power source voltage herein.
The semiconductor integrated circuit can adopt a trimming means capable of trimming the minimum value (determining a period in which the initial write voltage in the write operation is supplied) of the pulse width of the pulse-shaped voltage. Further, the trimming means is capable of trimming the rate of gradual increase in pulse width of the pulse-shaped voltage. When the initial write voltage is applied to one semiconductor integrated circuit chip in the same pulse width as that in another semiconductor integrated circuit chip, needless write and verify operations in which the threshold voltage substantially remains unchanged virtually, must be done many times, so that the efficiency of writing might be reduced greatly. If the minimum write voltage pulse width can be trimmed, then the differences in characteristic between memory cells due to process variations can be rendered uniform or optimized between semiconductor integrated circuit chips like flash memory chips. Namely, the amounts of shifts of threshold voltages of memory cells are considered to subtly differ from each other due to the process variations or the like even if the write voltages are the same. Allowing adjustments to the difference in such characteristic in an inspection process,such as a wafer process of a semiconductor integrated circuit like a flash memory chip, is important to make high-speed write possible.
Incidentally, a trimming means for trimming or adjusting the minimum value of the pulse-shaped voltage or the rate of gradual increase in pulse-shaped voltage can be adopted according to the form of the memory cell. array.
A semiconductor integrated circuit, such as a flash memory device, can be applied to a data processing system used to constitute a digital still camera. Namely, the data processing system includes an image sensing means, the semiconductor integrated circuit, and a mode control means for providing instructions for allowing the semiconductor integrated circuit to sequentially store image data obtained by the image sensing means in a first operating mode and for causing the semiconductor integrated. circuit to rewrite the image data stored in the semiconductor integrated circuit in the first operating mode to multivalued data in a second operating mode, using a period in which an imaging process of the image sensing means is brought to a halt.
A semiconductor integrated circuit, such as a flash memory device, also can be applied to a data processing system for constituting a PC card. Namely, the data processing system for constituting the PC card includes the semiconductor integrated circuit, like a flash memory, and a mode control means for setting a write operation for the semiconductor integrated circuit as a first operating mode upon supply of an external power source to the PC card and all owing the semiconductor integrated circuit to rewrite data written into the semiconductor integrated circuit in the first operating mode to multivalued data in a second operating mode in response to the cutoff of the supply of the external power source to the PC card.
This type of data processing system is capable of implementing the writing of data into each of the non-volatile memory cells of a semiconductor integrated circuit,like a flash memory, at high speed and is capable of improving the reliability of retention of the data stored therein.